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DescriptionQ705
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Q705DVASIC interview problem

Reset during an outstanding item

TechniquesUVMPull protocol handshake
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Format4 choices
01

Problem

A driver receives req with get_next_item. Reset asserts while it is driving, and the reset branch returns to the top of the loop without calling item_done. A sequence is blocked in finish_item. What is the root cause?

02

Answer choices (4)