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Reset during an outstanding item

MediumUVM ComponentsSystemVerilog

A driver receives req with get_next_item. Reset asserts while it is driving, and the reset branch returns to the top of the loop without calling item_done. A sequence is blocked in finish_item. What is the root cause?

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Answer choices

  1. A. get_next_item copies req by value and reset erased that copy
  2. B. finish_item can run only during build_phase
  3. C. Reset automatically flushes the sequencer, so the sequence is waiting on an unrelated objection
  4. D. finish_item waits for the driver's item_done, so abandoning the outstanding grant leaves both sequencer and sequence blocked
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UVM ComponentsSequencer-driver connection→UVM ComponentsGet_next_item and item_done→
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