DescriptionQ704
Q704DVASIC interview problem
Monitor an independently stalled binary adder
TechniquesDVStream monitorScoreboardFramingBackpressure
DifficultyHard
TopicReference Models
LanguageSystemVerilog
Requirements5 checkpoints
01
Problem
Verify a serial adder whose A and B operand frames handshake independently and whose least-significant-bit-first (LSB-first) sum frame can stall. Reconstruct accepted operands and check every accepted output bit and last marker.
Example input and output
Use this case to check your interpretationInput
A=3 arrives LSB-first as [1,1]; B=1 arrives independently as [1]; output ready stalls after its first beatOutput
expected sum bits=[0,0,1] with last only on the third accepted bitExplanation
3+1=4 requires the final carry bit; independent operand handshakes and the output stall do not advance any unsampled index.
02
Requirements (5)
- Advance each operand's bit index only on that channel's valid-ready handshake and close a frame only when its last bit is accepted.
- Pair completed A and B frames in order and predict max(length A, length B) bits plus a final bit only when carry remains.
- Compare sum bits only on accepted output transfers and require sum_last exactly on the final expected bit.
- Reject overlength, nested, or next-frame traffic while the base DUT still owns a pair.
- Flush partial operands and expectations on reset and require stalled output data and framing to remain stable.