1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ682

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Q682DesignNVIDIAASIC interview problem

Implement a divide-by-four clock model

TechniquesDesignSystemVerilogCounterClocking

DifficultyEasy

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

For simulation or FPGA-style RTL, divide clk by four with a resettable two-bit counter. Also state the safe ASIC implementation rule for a generated clock.

Starting declarationSystemVerilog

input logic clk, rst_n;
output logic clk_div4;

Example input and output

Use this case to check your interpretation

Input

Counter starts at 00; apply four rising edges

Output

counter: 01,10,11,00; clk_div4: 0,1,1,0

Explanation

The counter MSB completes one period for every four source-clock periods.

Requirements (4)

Clear the two-bit counter with active-low asynchronous reset.
Increment it on every rising edge while reset is inactive.
Drive clk_div4 from counter bit 1 for a 50 percent steady-state duty cycle.
For ASIC clock consumers, require an approved clock-generation primitive and generated-clock constraint.