DescriptionQ677
Q677DVASIC interview problem
Verify a decimal palindrome checker
TechniquesDVReference modelSigned arithmeticLatencyReset
DifficultyMedium
TopicReference Models
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Verify a single-request block that reports whether a signed 32-bit value reads the same forward and backward in ordinary decimal notation.
Starting declarationSystemVerilog
logic clk, rst_n, start;
logic signed [31:0] number;
logic busy, done;
logic request_error, is_palindrome;
parameter int MAX_LATENCY = 12;Example input and output
Use this case to check your interpretationInput
accept number=12321; change live input bus to 99 while busyOutput
palindrome=1 for captured 12321; exactly one done pulseExplanation
The accepted request is snapshotted, so later input changes cannot alter the decimal reversal result.
02
Requirements (4)
- Accept a request only when start is high and busy is low, and snapshot the accepted number.
- Treat every negative number as false, zero as true, and trailing-zero values such as 10 as false.
- Require exactly one done pulse within 1 through MAX_LATENCY cycles unless reset cancels the request.
- Compare both completion outputs, ignore later input changes, and cover busy starts and reset during work.