DescriptionQ661
Q661DesignArchAppleASIC interview problem
Four-bit adder and synthesized structure
TechniquesDesignArchAdderCarry
DifficultyEasy
TopicRTL Arithmetic
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Write a synthesizable 4-bit unsigned adder with carry-in and carry-out, then explain the ripple-carry structure and its critical path.
Module declarationSystemVerilog
module add4 (
input logic [3:0] a, b,
input logic cin,
output logic [3:0] sum,
output logic cout
);Example input and output
Use this case to check your interpretationInput
a=4'd15, b=4'd1, cin=0Output
cout=1, sum=4'd0Explanation
The fifth result bit must not be discarded.
02
Requirements (4)
- Preserve the complete 5-bit result.
- Describe a four-stage full-adder carry chain.
- Explain propagate and generate terms.
- Contrast ripple carry with a carry-lookahead structure.