Hardware interview practice

Four-bit adder and synthesized structure

EasyRTL ArithmeticSystemVerilog

Write a synthesizable 4-bit unsigned adder with carry-in and carry-out, then explain the ripple-carry structure and its critical path.

Starting point

Question code

module add4 (
  input  logic [3:0] a, b,
  input  logic       cin,
  output logic [3:0] sum,
  output logic       cout
);

Reviewed example

Input

a=4'd15, b=4'd1, cin=0

Expected output

cout=1, sum=4'd0

The fifth result bit must not be discarded.

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