DescriptionQ600
Q600DVMetaASIC interview problem
Out-of-order scoreboard for a 2-by-4 router
TechniquesDVUVMScoreboardOut-of-order
DifficultyHard
TopicUVM
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A single-clock router has two input streams and four output streams. IDs are unique while outstanding, but different packets may exit in any order. Build a UVM scoreboard that matches by ID, processes same-cycle inputs before outputs, and reports leftovers at end of test.
Starting declarationSystemVerilog
input item: {cycle, id[7:0], dst[1:0], payload[31:0]}
output item: {cycle, id[7:0], port[1:0], payload[31:0]}
IDs are unique while outstandingExample input and output
Use this case to check your interpretationInput
Cycle 20 accepts id=10,dst=3,payload=AA and id=11,dst=0,payload=BB; outputs later arrive id=11 then id=10Output
No scoreboard error and the expected associative array becomes emptyExplanation
Both packets are found by ID, so their cross-ID completion order is irrelevant; each still must match its own route and payload.
02
Requirements (4)
- Store one expected record keyed by ID on every accepted input and reject a duplicate outstanding ID.
- For every output, require an existing ID, matching port/destination and payload, then remove exactly that ID.
- Callbacks enqueue timestamped events; for each sampled cycle process all inputs before that cycle's outputs, while allowing outputs in any ID order.
- Report unexpected, duplicate, or mismatched outputs immediately, and every outstanding ID in check_phase.