DescriptionQ549
Q549DesignQualcommASIC interview problem
Pack four display pixels with backpressure
TechniquesDesignRTLSystemVerilogPackFour
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A display block receives 8-bit pixels and emits one 32-bit little-endian word for every four accepted pixels. Design the ready/valid packer in synthesizable SystemVerilog.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic pix_valid; input logic [7:0] pix;
output logic pix_ready;
output logic word_valid; output logic [31:0] word;
input logic word_ready;Example input and output
Use this case to check your interpretationInput
Accept pixels 0x11, 0x22, 0x33, and 0x44 in that order.Output
word = 32'h44332211 and word_valid = 1.Explanation
Little-endian packing places the first pixel in bits 7:0 and the fourth in bits 31:24.
02
Requirements (4)
- Accept a pixel only on pix_valid && pix_ready and place the first through fourth pixels into word bits [7:0], [15:8], [23:16], and [31:24].
- Assert word_valid after the fourth accepted pixel and hold word and word_valid stable until word_ready is high.
- Whenever word_valid=1, drive pix_ready=0 even if the output transfers that cycle; accept the next group's first pixel no earlier than the following cycle.
- When rst_n is 0 at a rising edge, discard every partial group and clear word_valid.