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Hardware interview practice

Pack four display pixels with backpressure

MediumRTL DesignSystemVerilog

A display block receives 8-bit pixels and emits one 32-bit little-endian word for every four accepted pixels. Design the ready/valid packer in synthesizable SystemVerilog.

Starting point

Question code

input logic clk, rst_n;
input logic pix_valid; input logic [7:0] pix;
output logic pix_ready;
output logic word_valid; output logic [31:0] word;
input logic word_ready;
Reviewed example

Work through one case

Input
Accept pixels 0x11, 0x22, 0x33, and 0x44 in that order.
Expected output
word = 32'h44332211 and word_valid = 1.

Little-endian packing places the first pixel in bits 7:0 and the fourth in bits 31:24.

What to cover

Requirements

  1. Accept a pixel only on pix_valid && pix_ready and place the first through fourth pixels into word bits [7:0], [15:8], [23:16], and [31:24].
  2. Assert word_valid after the fourth accepted pixel and hold word and word_valid stable until word_ready is high.
  3. Whenever word_valid=1, drive pix_ready=0 even if the output transfers that cycle; accept the next group's first pixel no earlier than the following cycle.
  4. When rst_n is 0 at a rising edge, discard every partial group and clear word_valid.