DescriptionQ548
Q548DesignASIC interview problem
Shorten a critical path with pipelining
TechniquesCritical pathPipeliningFmaxValid alignment
DifficultyMedium
TopicTiming
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A four-operand W-bit sum is too slow as one long combinational expression. Re-architect it as a two-stage pipeline that accepts new inputs every cycle and carries a valid bit to the output.
Example input and output
Use this case to check your interpretationInput
W=8; accept a=200,b=100,c=50,d=10 at cycle0Output
10-bit sum=360 with out_valid at cycle2Explanation
Stage one registers widened partials 300 and 60, and stage two registers their full sum while later transactions may enter every cycle.
02
Requirements (4)
- Add enough width to preserve the full mathematical sum.
- Register two pairwise partial sums, then register their final sum.
- Accept one transaction per cycle and produce results at fixed two-cycle latency.
- Explain that latency increases even though throughput can remain one result per cycle.