DescriptionQ544
Q544DVASIC interview problem
Verify a framed cache-line rotator
TechniquesDVDesignFramingBackpressureReference model
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Requirements5 checkpoints
01
Problem
Write a frame oracle and core output properties for a streaming cache-line rotator that samples count and right-shift metadata on the first accepted beat.
Example input and output
Use this case to check your interpretationInput
first accepted beat declares count=4,right_shift=1; frame data=[A,B,C,D] with correct last markerOutput
output beats=[D,A,B,C] with first/last metadata on the proper endpointsExplanation
Shift one modulo four rotates the snapshotted legal frame right and every beat is compared only on an output handshake.
02
Requirements (5)
- Assemble transactions only from input handshakes and sample count and shift on the first accepted beat.
- Predict a right rotation by shift modulo count; count zero produces one all-zero success beat, while legal nonempty frames produce exactly count beats.
- Classify every first/last marker and accepted-beat count as bad-first, oversized-count, early-last, or late/extra; malformed input predicts one coded zero beat.
- Assert output stability under backpressure and no internal gap when the receiver remains ready.
- Treat input draining, transaction admission, reset epochs, and coverage as follow-up monitor/scoreboard design questions.