1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ532

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Q532DesignNVIDIAASIC interview problem

Find fmax for a half-cycle timing path

TechniquesDesignTimingSTACalculation

DifficultyMedium

TopicStatic Timing Analysis

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A falling-edge launch to rising-edge capture path has -50 ps setup slack at a 900 ps period. Assume every non-period term stays fixed. Find the shortest passing period and maximum frequency.

Starting declarationSystemVerilog

T_old = 900 ps
available half-cycle = T_old / 2
setup slack = -50 ps

Example input and output

Use this case to check your interpretation

Input

T=900 ps and slack=-50 ps

Output

Tmin=1000 ps, fmax=1 GHz

Explanation

The current 450 ps half-cycle needs 50 ps more, so the required half-cycle is 500 ps and the full period is 1000 ps.

Requirements (4)

Use the T/2 falling-to-rising setup budget.
Add the 50 ps deficit to the existing half-cycle budget.
Solve for the full period that gives zero slack.
Report period in ps and frequency in GHz.