DescriptionQ051
Q051DesignArchMicronASIC interview problem
Enforce simplified per-bank command timing
TechniquesRTL DesignRTL / Microarchitectureenforce simplified per-bank command timing
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A four-bank controller accepts or rejects ACT, READ, and PRE commands from one input slot each cycle. Implement the synthesizable bank-state and timing guard.
Starting declarationSystemVerilog
input logic clk, rst_n, cmd_valid;
input logic [1:0] cmd, bank; // ACT=0, READ=1, PRE=2
output logic accept, reject;Example input and output
Use this case to check your interpretationInput
Accept ACT bank0 at C0, then present READ bank0 at C2 and again at C3.Output
The C2 READ is rejected and the C3 READ is accepted.Explanation
The ACT-to-READ guard requires three full cycles after C0, so the bank's read cooldown expires only for the C3 command.
02
Requirements (4)
- After reset all banks are closed and an ACT is immediately legal. accept and reject are combinational functions of cmd_valid, cmd, bank, and registered pre-edge bank/timestamp state; both are 0 when cmd_valid=0, and cmd_valid=1 with cmd=3 gives accept=0 and reject=1.
- ACT is legal only for a closed bank and at least two full cycles after its last accepted PRE; READ is legal only for an open bank and at least three full cycles after its accepted ACT.
- PRE is legal only for an open bank and at least two full cycles after its most recent accepted READ; if no READ occurred since ACT, PRE is legal immediately.
- On a rising edge, update open/closed state and timestamps only when the pre-edge combinational accept is 1. reject, cmd_valid=0, or cmd=3 changes no state; rst_n=0 on the edge has priority and resets every bank.