Skip to the selected question
ASIC.FYI

ASIC Question Bank

1,000+ hardware interview questions
Question bank1110 results
  1. Easy
  2. Easy
  3. Medium
  4. Medium
  5. Medium
  6. Medium
  7. Easy
  8. Easy
  9. Easy
  10. Easy
  11. Easy
  12. Easy
  13. Easy
  14. Easy
  15. Medium
  16. Easy
  17. Medium
  18. Easy
  19. Hard
  20. Medium
  21. Medium
  22. Easy
  23. Medium
  24. Medium
  25. Medium
  26. Easy
  27. Medium
  28. Medium
  29. Easy
  30. Easy
  31. Medium
  32. Medium
  33. Hard
  34. Easy
  35. Medium
  36. Hard
  37. Easy
  38. Medium
  39. Hard
  40. Medium
  41. Medium
  42. Easy
  43. Medium
  44. Medium
  45. Medium
  46. Easy
  47. Hard
  48. Easy
  49. Easy
  50. Easy
DescriptionQ050
Page ↗
Q050DVASIC interview problem

Read Returns Data From the Wrong Register

TechniquesDVWaveform DebuggingRegisters
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. A read of address 0x14 is accepted at C2; expected_data is 0x55, but actual_data is 0xAA. Rule to apply: The response mux is selected by the internal one-hot signal reg_sel. reg_sel[1] selects address 0x14 and data 0x55; reg_sel[0] selects address 0x10 and data 0xAA. Which signal should be traced next to test for an address-decode error?

Waveform for Read Returns Data From the Wrong Register. Signals: rd_valid, rd_ready, rd_addr, rsp_valid, expected_data, actual_data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)