DescriptionQ493
Q493DVArchIntelASIC interview problem
Two-core MESI reference model
TechniquesArchMicroarchitectureInterconnectTwo-CoreMesi
DifficultyMedium
TopicComputer Architecture
LanguageC++
Requirements4 checkpoints
01
Problem
A checker models one cache line in two cores with only read, write, and evict operations. Write a C++ state-transition function for the model.
Starting declarationC++
enum State { I, S, E, M };
enum Op { READ, WRITE, EVICT };
bool step(State s[2], unsigned core, Op op);Example input and output
Use this case to check your interpretationInput
Start in {I, I} and apply READ from core 0.Output
The state pair becomes {E, I}.Explanation
With no other cached copy, the reading core receives the line exclusively rather than sharing it.
02
Requirements (4)
- Assume the input pair is one legal MESI state: II, EI, IE, SI, IS, SS, MI, or IM; behavior for an illegal initial pair is outside this model. Reject core>1, preserve state, and return false; return true for an accepted operation.
- READ from I becomes E if the other core is I, otherwise both valid copies become S; READ from S/E/M changes nothing.
- WRITE makes the selected core M and the other core I, regardless of the selected core's prior state.
- EVICT makes only the selected core I; after every accepted operation, reject no legal state and preserve the MESI single-writer invariant.