1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ467

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Q467ArchDesignNVIDIAASIC interview problem

Balance a pipeline with one added register

TechniquesArchDesignPipelinePerformance

DifficultyMedium

TopicComputer Architecture

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A three-stage pipeline has logic delays 1.0 ns, 3.2 ns, and 0.8 ns plus 0.2 ns register overhead per stage. Split the middle logic into two 1.6 ns stages and quantify the result.

Starting declarationSystemVerilog

logic_delays = {1.0, 3.2, 0.8} ns
register_overhead = 0.2 ns
middle split = {1.6, 1.6} ns

Example input and output

Use this case to check your interpretation

Input

Original logic {1.0,3.2,0.8} ns with 0.2 ns overhead

Output

Original fmax about 294 MHz; split fmax about 556 MHz; latency increases by one cycle

Explanation

The critical period drops from 3.4 ns to 1.8 ns after the split.

Requirements (4)

Compute the original critical period and ideal fmax.
Insert exactly one register to split the middle stage.
Compute every new stage period and new ideal fmax.
State the latency increase and need to retime control and bypass paths.