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asic.fyi

Hardware interview practice

Balance a pipeline with one added register

MediumComputer ArchitectureSystemVerilog

A three-stage pipeline has logic delays 1.0 ns, 3.2 ns, and 0.8 ns plus 0.2 ns register overhead per stage. Split the middle logic into two 1.6 ns stages and quantify the result.

Starting point

Question code

logic_delays = {1.0, 3.2, 0.8} ns
register_overhead = 0.2 ns
middle split = {1.6, 1.6} ns
Reviewed example

Work through one case

Input
Original logic {1.0,3.2,0.8} ns with 0.2 ns overhead
Expected output
Original fmax about 294 MHz; split fmax about 556 MHz; latency increases by one cycle

The critical period drops from 3.4 ns to 1.8 ns after the split.

What to cover

Requirements

  1. Compute the original critical period and ideal fmax.
  2. Insert exactly one register to split the middle stage.
  3. Compute every new stage period and new ideal fmax.
  4. State the latency increase and need to retime control and bypass paths.