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DescriptionQ456
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Q456DesignArchIntelASIC interview problem

Convert DDR Clock Rate into Bus Bandwidth

TechniquesDesignArchClockingDDRMemory
DifficultyEasy
TopicTiming
LanguageSystemVerilog
Format4 choices
01

Problem

Two ideal 64-bit memory buses use an 800 MHz clock. One is single-data-rate; the other transfers data on both clock edges. Ignore command overhead and idle cycles. Which peak-rate comparison is correct?

02

Answer choices (4)