DescriptionQ430
Q430DesignMicronASIC interview problem
Control entry to and exit from memory self-refresh
TechniquesDesignLow powerPower sequencingControlEntry
DifficultyMedium
TopicLow Power Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A memory wrapper receives a low-power request and a wake request while an external memory supplies enter and exit acknowledgements. Implement the four-state self-refresh controller.
Starting declarationSystemVerilog
input logic clk, rst_n, sleep_req, wake_req;
input logic enter_ack, exit_ack;
output logic enter_req, exit_req;
output logic cmd_enable, in_self_refresh;Example input and output
Use this case to check your interpretationInput
Assert sleep_req at C0 and enter_ack at C2.Output
cmd_enable is 0 from C0, enter_req is held until C2, and in_self_refresh is 1 after C2.Explanation
The controller quiesces commands when entry starts and does not enter self-refresh until the acknowledgement is sampled.
02
Requirements (4)
- Reset enters ACTIVE with cmd_enable=1 and all other outputs 0. In ACTIVE, sleep_req moves to ENTER and immediately makes cmd_enable=0.
- In ENTER, hold enter_req=1 until enter_ack, then enter SELF_REFRESH with in_self_refresh=1 and both request outputs 0.
- In SELF_REFRESH, ignore sleep_req; wake_req moves to EXIT, clears in_self_refresh, and asserts exit_req until exit_ack.
- After exit_ack return to ACTIVE with cmd_enable=1; ignore wake_req outside SELF_REFRESH and do not impose a timeout.