DescriptionQ429
Q429DVASIC interview problem
Compare values safely with X and Z
TechniquesFour-state logicCase equalityX propagation
DifficultyEasy
TopicVerification Utilities
LanguageSystemVerilog
Requirements3 checkpoints
01
Problem
Implement exact four-state equality and a known-value equality policy for two 32-bit logic vectors.
Example input and output
Use this case to check your interpretationInput
a=32'h0000_00XZ, b=32'h0000_00XZ, c=32'h0000_0009Output
equal_exact_4state(a,b)=1; equal_when_known(a,b)=0; equal_when_known(c,c)=1Explanation
Case equality accepts matching X/Z positions, while known-value equality first rejects any operand containing an unknown or high-impedance bit.
02
Requirements (3)
- Exact equality must allow matching X and Z bits.
- Known-value equality must reject either operand when it contains X or Z.
- Both helpers must return a two-state bit result.