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Hardware interview practice

Compare values safely with X and Z

EasyVerification UtilitiesSystemVerilog

Implement exact four-state equality and a known-value equality policy for two 32-bit logic vectors.

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Reviewed example

Work through one case

Input
a=32'h0000_00XZ, b=32'h0000_00XZ, c=32'h0000_0009
Expected output
equal_exact_4state(a,b)=1; equal_when_known(a,b)=0; equal_when_known(c,c)=1

Case equality accepts matching X/Z positions, while known-value equality first rejects any operand containing an unknown or high-impedance bit.

What to cover

Requirements

  1. Exact equality must allow matching X and Z bits.
  2. Known-value equality must reject either operand when it contains X or Z.
  3. Both helpers must return a two-state bit result.
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