DescriptionQ379
Q379DesignMicronASIC interview problem
Bridge a sticky memory-error alarm across clocks
TechniquesDesignCDCResetBridgeA
DifficultyMedium
TopicCDC and Reset
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A fast memory-test clock may detect an error while a slower service clock is busy. The alarm must not be lost and only one alarm may be pending. Implement the request/acknowledge alarm bridge in SystemVerilog.
Starting declarationSystemVerilog
input logic src_clk, dst_clk, rst_n;
input logic src_error; output logic src_pending;
output logic dst_alarm; input logic dst_clear;Example input and output
Use this case to check your interpretationInput
Pulse src_error once and leave dst_clear low.Output
req and src_pending stay high, dst_alarm becomes and remains high, and ack stays low.Explanation
The four-phase request remains pending until the destination explicitly clears the sticky alarm and raises acknowledgement.
02
Requirements (4)
- Implement internal four-phase req/ack levels. In the source domain, src_error sets req=1 and src_pending=1; later src_error pulses while pending are coalesced into that request.
- Synchronize req through two destination flops. When a new synchronized req=1 is seen with ack=0, set dst_alarm. A dst_clear on that same edge loses to the set. On a later edge with dst_alarm=1, req=1, and dst_clear=1, clear dst_alarm and set ack=1.
- Synchronize ack through two source flops. When synchronized ack becomes 1, lower req but keep src_pending=1. The destination holds ack=1 until synchronized req becomes 0, then lowers ack; only after synchronized ack returns to 0 may the source clear src_pending.
- rst_n asynchronously clears req, ack, both synchronizer chains, src_pending, and dst_alarm. Reset has priority; no combinational path crosses domains, and dst_clear while dst_alarm=0 has no effect.