DescriptionQ374
Q374DesignAMDASIC interview problem
Synchronize and filter an asynchronous alarm
TechniquesDesignCDCResetSynchronizeAnd
DifficultyMedium
TopicCDC and Reset
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
An asynchronous thermal alarm may chatter. The destination must synchronize it and change its output only after three equal synchronized samples. Implement the two-flop synchronizer and three-sample filter in SystemVerilog.
Starting declarationSystemVerilog
input logic clk, rst_n, alarm_async;
output logic alarm_filtered;Example input and output
Use this case to check your interpretationInput
Starting with alarm_filtered = 0, present second-stage synchronized samples 1, 1, 1.Output
alarm_filtered changes to 1 on the third sample.Explanation
Three consecutive equal synchronized samples satisfy the assertion threshold exactly on the final sample.
02
Requirements (4)
- Pass alarm_async through two destination flip-flops before the filter uses it.
- Set alarm_filtered after three consecutive second-stage samples of one; clear it after three consecutive samples of zero.
- A sample opposite to the current run restarts the run count at one for the new value.
- Synchronous active-low reset clears both synchronizer stages, the run state, the count, and alarm_filtered.