Hardware interview practice
Synchronize and filter an asynchronous alarm
An asynchronous thermal alarm may chatter. The destination must synchronize it and change its output only after three equal synchronized samples. Implement the two-flop synchronizer and three-sample filter in SystemVerilog.
Starting point
Question code
input logic clk, rst_n, alarm_async;
output logic alarm_filtered;Reviewed example
Work through one case
Input
Starting with alarm_filtered = 0, present second-stage synchronized samples 1, 1, 1.Expected output
alarm_filtered changes to 1 on the third sample.Three consecutive equal synchronized samples satisfy the assertion threshold exactly on the final sample.
What to cover
Requirements
- Pass alarm_async through two destination flip-flops before the filter uses it.
- Set alarm_filtered after three consecutive second-stage samples of one; clear it after three consecutive samples of zero.
- A sample opposite to the current run restarts the run count at one for the new value.
- Synchronous active-low reset clears both synchronizer stages, the run state, the count, and alarm_filtered.