DescriptionQ372
Q372DesignASIC interview problem
Debounce a noisy active-low button
TechniquesDebouncerSynchronizerCounterOne-shot pulse
DifficultyMedium
TopicFSMs
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Design a robust active-low push-button debouncer. Emit exactly one clock-wide btn_pressed_tick per physical press, tolerate fast bounce and slow release jitter, and re-arm only after a stable release.
Example input and output
Use this case to check your interpretationInput
STABILITY_CYCLES=3; synchronized active-low samples=[0,0,1,0,0,0,0,1,1,1]Output
one btn_pressed_tick on the third consecutive low; rearmed only on the third consecutive highExplanation
Early bounce resets the press counter, the extra low cannot retrigger, and stable release completes re-arming.
02
Requirements (4)
- Synchronize the asynchronous button before using it in the FSM.
- Require STABILITY_CYCLES consecutive samples for both press and release.
- Pulse once after a stable press and never retrigger until a stable release completes.
- Support STABILITY_CYCLES = 1 without a zero-width counter.