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Hardware interview practice

Debounce a noisy active-low button

MediumFSMsSystemVerilog

Design a robust active-low push-button debouncer. Emit exactly one clock-wide btn_pressed_tick per physical press, tolerate fast bounce and slow release jitter, and re-arm only after a stable release.

Reviewed example

Work through one case

Input
STABILITY_CYCLES=3; synchronized active-low samples=[0,0,1,0,0,0,0,1,1,1]
Expected output
one btn_pressed_tick on the third consecutive low; rearmed only on the third consecutive high

Early bounce resets the press counter, the extra low cannot retrigger, and stable release completes re-arming.

What to cover

Requirements

  1. Synchronize the asynchronous button before using it in the FSM.
  2. Require STABILITY_CYCLES consecutive samples for both press and release.
  3. Pulse once after a stable press and never retrigger until a stable release completes.
  4. Support STABILITY_CYCLES = 1 without a zero-width counter.