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DescriptionQ362
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Q362DVDesignAMDASIC interview problem

Make Mixed Signed Arithmetic Explicit

TechniquesDesignSystemVerilog
DifficultyMedium
TopicSV
LanguageSystemVerilog
Format4 choices
01

Problem

`s` is signed 8-bit value -2 and `u` is unsigned 8-bit value 130. A 9-bit signed result must be the mathematical sum +128, not the wrapped 8-bit value -128. Which expression explicitly extends both operands into the intended signed 9-bit domain?

02

Answer choices (4)