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Make Mixed Signed Arithmetic Explicit

MediumSystemVerilogSystemVerilog

`s` is signed 8-bit value -2 and `u` is unsigned 8-bit value 130. A 9-bit signed result must be the mathematical sum +128, not the wrapped 8-bit value -128. Which expression explicitly extends both operands into the intended signed 9-bit domain?

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Answer choices

  1. A. `s + u` with no casts or extension because the signed operand always controls the expression.
  2. B. `{1'b0,s} + {1'b0,u}` because zero-extension is correct for every signed operand.
  3. C. `$signed(s + u)` because casting the final possibly narrow mixed-sign result repairs its width and value.
  4. D. `$signed({s[7],s}) + $signed({1'b0,u})`
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