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DescriptionQ034
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Q034DVASIC interview problem

APB Access Starts Without a Setup Cycle

TechniquesDVWaveform DebuggingAPB
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. C1-C2 show a legal reference transfer; after the idle C3 edge, a second APB transfer begins. Rule to apply: A transfer must have a setup cycle with PSEL=1 and PENABLE=0, followed by an access cycle with PSEL=1 and PENABLE=1. What is wrong with the transfer?

Waveform for APB Access Starts Without a Setup Cycle. Signals: PSEL, PENABLE, PREADY, PADDR. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)