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Hardware interview practice

APB Access Starts Without a Setup Cycle

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. C1-C2 show a legal reference transfer; after the idle C3 edge, a second APB transfer begins. Rule to apply: A transfer must have a setup cycle with PSEL=1 and PENABLE=0, followed by an access cycle with PSEL=1 and PENABLE=1. What is wrong with the transfer?

Waveform for APB Access Starts Without a Setup Cycle. Signals: PSEL, PENABLE, PREADY, PADDR. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. PREADY is low during a wait state.
  2. B. PADDR stays unchanged until completion.
  3. C. PSEL remains high during the access.
  4. D. PENABLE rises with PSEL, so there is no setup cycle.