ASIC Question Bank

A DUT always_ff samples raw req on each posedge. The driver uses a #0 clocking-block output and holds req at 1 through the following posedge. At which posedge can the DUT first sample 1?

clocking cb @(posedge clk);
  output #0 req;
endclocking

// Driver: req remains 1 through the following posedge.
@(vif.cb);
vif.cb.req <= 1;