Hardware interview practice

Clocking-block output timing

HardVerification UtilitiesSystemVerilog

A DUT always_ff samples raw req on each posedge. The driver uses a #0 clocking-block output and holds req at 1 through the following posedge. At which posedge can the DUT first sample 1?

Starting point

Question code

clocking cb @(posedge clk);
  output #0 req;
endclocking

// Driver: req remains 1 through the following posedge.
@(vif.cb);
vif.cb.req <= 1;

Choose one

Answer choices

A. The same posedge that awakened @(vif.cb)
B. The next posedge, because the same-edge DUT sampling precedes the clocking output drive
C. Half a cycle later, regardless of the next edge
D. Never; clocking-block outputs cannot drive interface signals