DescriptionQ320
Q320DVASIC interview problem
Verify unique zero-sum triplets
TechniquesDV3SumScoreboardStreamingBackpressure
DifficultyMedium
TopicReference Models
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Verify an accelerator that streams every unique sorted three-value combination whose widened sum is zero, in strict dictionary order.
Interface declarationSystemVerilog
interface triplet_if #(int N=12, W=12)(input logic clk);
logic rst_n, req_valid, req_ready;
logic [3:0] count;
logic signed [W-1:0] value[N];
logic out_valid, out_ready, out_first, out_last, out_empty, out_error;
logic signed [W-1:0] a, b, c;
endinterfaceExample input and output
Use this case to check your interpretationInput
values=[-1,0,1,2,-1,-4]Output
beats=(-1,-1,2) first=1 last=0; (-1,0,1) first=0 last=1Explanation
Index triples are normalized and deduplicated by values, then the two unique solutions are streamed in dictionary order.
02
Requirements (4)
- Enumerate all index triples from an accepted request, sort each value triple, and deduplicate by values rather than indexes.
- Sort expected triples by a, then b, then c and check exact first/last markers.
- Use one defined special beat for no-solution and another for invalid count, with all zero payload fields.
- Block another request until final acceptance, hold stalled fields stable, enforce progress, and cancel on reset.