DescriptionQ308
Q308DVDesignASIC interview problem
Packages
TechniquesSystemVerilogElaboration and reuse
DifficultyEasy
TopicSV
LanguageSystemVerilog
Format4 choices
01
Problem
Which statement about word_t is correct?
Starting declarationSystemVerilog
package p;
parameter int W = 8;
typedef logic [W-1:0] word_t;
endpackage
module m; p::word_t x; endmodule02