DescriptionQ286
Q286ArchMicronASIC interview problem
Schedule four credited memory clients fairly
TechniquesArchMicroarchitectureInterconnectSchedulefairly
DifficultyHard
TopicComputer Architecture
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Four memory-side interconnect clients request one shared command slot. Each begins with two credits and returns at most one credit per cycle. Implement the round-robin credited scheduler in synthesizable SystemVerilog.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic [3:0] req, credit_return;
output logic [3:0] grant;
output logic [2:0] credit[4];Example input and output
Use this case to check your interpretationInput
After reset, req=4'b1111 for four cycles with no credit returns.Output
grants are 0001, 0010, 0100, 1000 and every client finishes with one credit.Explanation
Round-robin begins at client 0, advances after each grant, and each selected request consumes one of its initial two credits.
02
Requirements (4)
- Reset sets each credit to 2, the round-robin start pointer to 0, and grant to 0. Credits saturate at 7.
- For each cycle, first form post-return credit by adding credit_return, then a channel is eligible exactly when req=1 and its post-return credit is nonzero.
- Grant at most one eligible channel, choosing the first from the current pointer with wraparound; a grant consumes one post-return credit on that same edge.
- After a grant move the pointer to one past the winner; with no grant hold the pointer. Published credit after the edge includes both the return and any grant consumption.