DescriptionQ263
Q263DesignAppleASIC interview problem
Check reset-bounded delivery of asynchronous events
TechniquesDesignCDCResetCheckReset-Bounded
DifficultyMedium
TopicCDC and Reset
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A testbench observes a source event and the destination pulse from a reset-sensitive CDC channel. Only one event may be outstanding. Build a SystemVerilog checker that enforces delivery and discards work across either reset.
Starting declarationSystemVerilog
input logic src_clk, dst_clk;
input logic src_rst_n, dst_rst_n;
input logic src_event, dst_pulse;
output int unsigned errors;Example input and output
Use this case to check your interpretationInput
Accept an event at time 10; sample destination edges at 12, 16, and 20, with dst_pulse at 20.Output
The pulse is accepted at destination age 3 and errors remains 0.Explanation
Only destination edges strictly after acceptance increment age, placing the single pulse inside the legal age-2-through-age-5 window.
02
Requirements (4)
- Accept src_event only on a src_clk rising edge when both resets are high and no event is pending; a second event while pending increments errors once and is not queued.
- Count destination rising edges strictly after the accepted source edge; require exactly one dst_pulse on destination age 2 through 5 inclusive. If source and destination edges share a simulation time, process source acceptance first but label that destination sample age 0.
- A pulse with no pending event or at age 0 or 1 adds one error and clears the event. At age 5, a pulse is legal and wins over timeout; only absence of a pulse at age 5 adds the one timeout error and clears the event.
- Initialize errors to 0. Assertion of either reset immediately cancels pending work and clears its age but not prior errors; no pulse is expected until both resets are high again, and each sampled pulse while either reset is low increments errors.