1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ251

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Q251DVGoogleASIC interview problem

Constrain a unique aligned queue

TechniquesDVSystemVerilogQueueuniqueAlignment

DifficultyEasy

TopicSystemVerilog Constraints

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A sequence item needs four distinct word addresses inside a 64-byte register window. Write the SystemVerilog declaration and solver constraints for the address queue.

Class declarationSystemVerilog

class reg_seq_item;
  rand bit [7:0] addr_q[$];
  constraint size_c;
  constraint value_c;
endclass

Example input and output

Use this case to check your interpretation

Input

Randomize one item

Output

'{8'h00, 8'h04, 8'h20, 8'h3C} is legal

Explanation

The four values are in range, word-aligned, and unique. A repeated 8'h04 or an 8'h02 value is rejected by the solver.

Requirements (4)

Constrain addr_q.size() to exactly 4.
Constrain every element to the inclusive range 8'h00 through 8'h3C and to a multiple of four.
Constrain all four addresses to be unique without sorting them.
Check randomize() success before using the queue; no post_randomize repair is allowed.