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Hardware interview practice

Constrain a unique aligned queue

EasySystemVerilog ConstraintsSystemVerilog

A sequence item needs four distinct word addresses inside a 64-byte register window. Write the SystemVerilog declaration and solver constraints for the address queue.

Starting point

Question code

class reg_seq_item;
  rand bit [7:0] addr_q[$];
  constraint size_c;
  constraint value_c;
endclass
Reviewed example

Work through one case

Input
Randomize one item
Expected output
'{8'h00, 8'h04, 8'h20, 8'h3C} is legal

The four values are in range, word-aligned, and unique. A repeated 8'h04 or an 8'h02 value is rejected by the solver.

What to cover

Requirements

  1. Constrain addr_q.size() to exactly 4.
  2. Constrain every element to the inclusive range 8'h00 through 8'h3C and to a multiple of four.
  3. Constrain all four addresses to be unique without sorting them.
  4. Check randomize() success before using the queue; no post_randomize repair is allowed.