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DescriptionQ002
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Q002DVASIC interview problem

Valid Drops During a Stall

TechniquesDVWaveform DebuggingReady/valid
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is a rising clock edge. The source drives valid and data; the receiver drives ready. Rule to apply: If valid is 1 and ready is 0 at an edge, valid must remain 1 and data must remain unchanged at the next edge. A transfer occurs only when valid and ready are both 1. What is the root cause of the protocol failure?

Waveform for Valid Drops During a Stall. Signals: valid, ready, data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)