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DescriptionQ199
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Q199DVDesignASIC interview problem

Inactive, nonblocking assignment (NBA), and postponed regions

TechniquesSystemVerilogAdvanced scheduling
DifficultyHard
TopicSV
LanguageSystemVerilog
Format4 choices
01

Problem

What do the two messages print at the rising edge?

Starting declarationSystemVerilog
logic clk = 0, a = 0, b = 0;
always @(posedge clk) begin
  a <= 1;
  b <= a;
  #0 $display("D %0b %0b", a, b);
  $strobe("S %0b %0b", a, b);
end
initial #5 clk = 1;
02

Answer choices (4)