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Inactive, nonblocking assignment (NBA), and postponed regions

HardSystemVerilogSystemVerilog

What do the two messages print at the rising edge?

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Question code

logic clk = 0, a = 0, b = 0;
always @(posedge clk) begin
  a <= 1;
  b <= a;
  #0 $display("D %0b %0b", a, b);
  $strobe("S %0b %0b", a, b);
end
initial #5 clk = 1;
Choose one

Answer choices

  1. A. D 0 0; S 1 0
  2. B. D 1 0; S 1 0
  3. C. D 0 0; S 1 1
  4. D. Both messages are nondeterministic
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