1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ198

Page ↗

Q198DVAMDASIC interview problem

Constrain dependent burst fields

TechniquesDVSystemVerilogUVMConstrainDependent

DifficultyMedium

TopicSystemVerilog and UVM

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A UVM request describes an aligned burst that must remain inside one 4 KiB page. Write the SystemVerilog fields and constraints for address, beat size, and length.

Class declarationSystemVerilog

class burst_req extends uvm_sequence_item;
rand bit [31:0] addr; rand bit [2:0] size;
rand bit [7:0] len; // beats minus one
endclass

Example input and output

Use this case to check your interpretation

Input

addr = 32'h1000, size = 2, len = 15.

Output

The assignment is legal and describes 16 four-byte beats (64 bytes).

Explanation

The address is four-byte aligned, the burst ends inside its 4 KiB page, and 64 bytes is below the 128-byte limit.

Requirements (4)

Allow size values 0 through 4, giving bytes_per_beat=1<<size, and allow 1 through 16 beats so len is 0 through 15.
Constrain addr to be aligned to bytes_per_beat.
Constrain addr[11:0] + ((len+1)<<size) to be at most 4096, using a widened expression that cannot overflow.
Constrain the total transfer size to at most 128 bytes.