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Constrain dependent burst fields

MediumSystemVerilog and UVMSystemVerilog

A UVM request describes an aligned burst that must remain inside one 4 KiB page. Write the SystemVerilog fields and constraints for address, beat size, and length.

Starting point

Question code

class burst_req extends uvm_sequence_item;
rand bit [31:0] addr; rand bit [2:0] size;
rand bit [7:0] len; // beats minus one
endclass
Reviewed example

Work through one case

Input
addr = 32'h1000, size = 2, len = 15.
Expected output
The assignment is legal and describes 16 four-byte beats (64 bytes).

The address is four-byte aligned, the burst ends inside its 4 KiB page, and 64 bytes is below the 128-byte limit.

What to cover

Requirements

  1. Allow size values 0 through 4, giving bytes_per_beat=1<<size, and allow 1 through 16 beats so len is 0 through 15.
  2. Constrain addr to be aligned to bytes_per_beat.
  3. Constrain addr[11:0] + ((len+1)<<size) to be at most 4096, using a widened expression that cannot overflow.
  4. Constrain the total transfer size to at most 128 bytes.
Continue practicing
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