DescriptionQ195
Q195DesignArchAMDASIC interview problem
Build one-write/two-read memory from BRAM
TechniquesRTL DesignRTL / Microarchitecturebuild one-write/two-read memory from bram
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Two identical synchronous 1W1R BRAMs must implement a logical memory with one write and two independent reads. Implement the mirrored SystemVerilog wrapper with defined collision behavior.
Starting declarationSystemVerilog
input logic clk, we; input logic [7:0] waddr, raddr0, raddr1;
input logic [31:0] wdata;
output logic [31:0] rdata0, rdata1;Example input and output
Use this case to check your interpretationInput
Write address 5 with 32'h0000_00AA, then issue reads of address 5 on both read ports.Output
One edge after the reads, rdata0=rdata1=32'h0000_00AA.Explanation
The write is mirrored into both BRAM copies, and each registered read port retrieves the same defined logical location.
02
Requirements (4)
- Instantiate or infer two 256x32 1W1R memories and apply every write to both copies on the same rising edge.
- Use copy 0 for read address raddr0 and copy 1 for raddr1; both read outputs are registered with one-cycle latency.
- Define same-edge read/write to the same address as write-first, returning wdata on the matching read output.
- There is no reset for memory contents or read data; the testbench compares read outputs only after a defined location is written.