DescriptionQ192
Q192ArchGoogleASIC interview problem
Control a link with return credits
TechniquesArchitectureInterconnectFlow controlCredits
DifficultyMedium
TopicComputer Architecture
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A sender crosses a latency-heavy link into an eight-entry receiver buffer. One credit represents one free receiver entry. Design the sender credit counter and transfer rule.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic tx_valid;
output logic tx_ready;
input logic [31:0] tx_data;
input logic [3:0] credit_return;
output logic credit_error;
initial credits = 8;
maximum receiver entries = 8;Example input and output
Use this case to check your interpretationInput
credits=0, tx_valid=1, credit_return=2Output
accepted=0 on this edge; next credits=2; credit_error=0Explanation
tx_ready is based on the pre-edge zero count. Returned credits become usable only after the state update.
02
Requirements (4)
- Reset sets credits=8 and credit_error=0; tx_ready uses the pre-edge credit count.
- Compute raw=credits+credit_return-(tx_valid&&tx_ready) once per edge.
- Store raw only when it is 0 through 8 and credit_return<=8; otherwise hold credits and pulse credit_error.
- When credits is zero, accept no transfer on that edge even if credits return simultaneously.