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DescriptionQ184
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Q184DVASIC interview problem

Read-Only Register Changes on a Write

TechniquesDVWaveform DebuggingRegisters
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. status_ro is a read-only hardware status register, and a bus write to its address is accepted at C2. Rule to apply: Software writes must never change status_ro. With no hardware status event, its value must remain stable. Which read-only register assertion fails here?

Waveform for Read-Only Register Changes on a Write. Signals: hw_event, wr_valid, wr_ready, wr_addr, wr_data, status_ro. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)