Skip to question
asic.fyi

Hardware interview practice

Read-Only Register Changes on a Write

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. status_ro is a read-only hardware status register, and a bus write to its address is accepted at C2. Rule to apply: Software writes must never change status_ro. With no hardware status event, its value must remain stable. Which read-only register assertion fails here?

Waveform for Read-Only Register Changes on a Write. Signals: hw_event, wr_valid, wr_ready, wr_addr, wr_data, status_ro. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. wr_data must always be zero.
  2. B. A write to a read-only register must not change it when no hardware event occurs.
  3. C. A read-only register must toggle every cycle.
  4. D. wr_valid must remain high after an accepted write.