Skip to the selected question
ASIC.FYI

ASIC Question Bank

1,000+ hardware interview questions
Question bank1110 results
  1. Easy
  2. Easy
  3. Medium
  4. Medium
  5. Medium
  6. Medium
  7. Easy
  8. Easy
  9. Easy
  10. Easy
  11. Easy
  12. Easy
  13. Easy
  14. Easy
  15. Medium
  16. Easy
  17. Medium
  18. Easy
  19. Hard
  20. Medium
  21. Medium
  22. Easy
  23. Medium
  24. Medium
  25. Medium
  26. Easy
  27. Medium
  28. Medium
  29. Easy
  30. Easy
  31. Medium
  32. Medium
  33. Hard
  34. Easy
  35. Medium
  36. Hard
  37. Easy
  38. Medium
  39. Hard
  40. Medium
  41. Medium
  42. Easy
  43. Medium
  44. Medium
  45. Medium
  46. Easy
  47. Hard
  48. Easy
  49. Easy
  50. Easy
DescriptionQ018
Page ↗
Q018DVASIC interview problem

Counter Changes While Disabled

TechniquesDVWaveform Debugging
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

en and load are sampled before each rising edge, and count is shown immediately afterward. load remains 0 throughout this waveform. Rule to apply: load has priority over en and would replace count with a programmed value. When load=0, count increments by one for en=1 and holds for en=0. What is the first incorrect behavior?

Waveform for Counter Changes While Disabled. Signals: en, count, load. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)