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Hardware interview practice

Counter Changes While Disabled

EasyWaveform DebuggingSystemVerilog

en and load are sampled before each rising edge, and count is shown immediately afterward. load remains 0 throughout this waveform. Rule to apply: load has priority over en and would replace count with a programmed value. When load=0, count increments by one for en=1 and holds for en=0. What is the first incorrect behavior?

Waveform for Counter Changes While Disabled. Signals: en, count, load. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. count changes after C4 while en is 0.
  2. B. count fails to increment at C1.
  3. C. load is asserted at C2 and changes count to 6.
  4. D. count changes at C2 even though en is 0.